AIDA Meeting - STFC DL - 10 November 2009
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Present: SLT, DB, PCS, TB, RDP, IL
Apologies: PM, JS

Summary of meeting
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Budget
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ASIC
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IEEE Paper DB/SLT lead authors, 
Minimum measured LLD

ME 0.4%
LE 1.4%

FEE
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Mezzanine delayed due to manufacturing fault
Two PCBs delivered for mechanical tests - OK 
New delivery date PCBs -> assembler November 13
From assembler to DL the following week

SLT would lie early example of mezzanine PCB for
bond wire process tests (vibration frequency, force,
duration etc) wrt gold of mezzanine PCB

Ab initio tests - mezzanine+FEE64
If we have problems RAL will test mezzanine by itself

FEE tests continuing OK

Data from 16-bit ADC looks sensible

Timestamp each disc output *and* each data ready

Mechanical Design
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Commissioning Tests 
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Other
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Next meeting:  Friday 4 Deecember 11.00