AIDA Meeting - STFC DL - 11 March 2008
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Present:	TD, PCS, RDP, SRA, IL
		SLT, DB (RAL via link)

Summary of meeting
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AIDA simulations (integration with DESPEC simulations)

AIDA DSSD enclosure

AIDA Mechanical Design

ASIC Design Review

Confirmation I_L should be restricted to < 100nA /strip
Ballistic effects favour longer shaping times

	Time jitter

Require 0.4ns rms 
N.B. no x10 gain between CSPA and disc for fast timing
SLT/DB will review

	Crosstalk

Reduce strip - strip capacitance of kapton cable
ground planes x 2 + guard lines between signal lines
detector ~2pF/cm 
Limited control - increased tau, reduced C_inter
Increased data rates

	ac coupling

SLT/DB require leakage currents in ac coupling 

TD 1mm DSSSD test with conversion electrons risetime variations

TD  to determine timing OR How structured/delay

SLT/DB check implant/decay disc ops from ASIC
	currently 16 bit/disc ops

IL suggests signal from ASIC indicating when channel
is in reset to avoid problems with sampling ADC/MWD etc.

SLT/DB to consider implant-decay, implant-implant and decay-decay timing
sequences and resets

Coupling of CSPA to comparator (via x10 amp + clip/diff)

FEE Design Review




Next Meeting: 12 May 2008 13.00 STFC RAL