From S.L.Thomas@rl.ac.uk Mon May 12 11:30:45 2008
Date: Tue, 15 Apr 2008 17:24:43 +0100
From: "Thomas, SL (Stephen)" <S.L.Thomas@rl.ac.uk>
To: "Coleman-Smith, PJ (Patrick)" <p.j.coleman-smith@dl.ac.uk>,
     "Braga, D (Davide)" <D.Braga@rl.ac.uk>
Cc: Thomas Davinson <td@ph.ed.ac.uk>,
     "Lazarus, IH (Ian)" <i.h.lazarus@dl.ac.uk>
Subject: ADC drive

Patrick

We haven't started work yet on optimising the pre-amp buffer amplifiers.
There are existing circuits for unity gain buffers, based on designs for
other projects. It should be possible to achieve the full 2V output
range, to match the ADC range (driven single-ended). The problem is the
switched capacitor input of the ADC, with the requirement for
stabilisation within 10ns. We will need to run some simulations to see
what happens under realistic conditions.

The safest option for your PCB design is to include the external
op-amps, with single to differential conversion, which we know will
achieve the best ADC noise performance. If the ASIC buffers work well,
with good stabilisation, then it would be possible to make direct
connections from the outputs to the ADC inputs, bypassing the op-amps.
Your board layout could include a jumper to allow this connection to be
made, with the op-amps omitted from the board to save power.

Steve




> -----Original Message-----
> From: Coleman-Smith, PJ (Patrick) 
> Sent: 10 April 2008 17:04
> To: Thomas, SL (Stephen); Braga, D (Davide)
> Cc: 'Thomas Davinson'; Lazarus, IH (Ian)
> Subject: 
> 
> 
> Hi Steve and Davide,
> I'm working on the FEE and would be grateful for your help.
> 
> In the ASIC specification 1.3 you suggest the ASIC could 
> drive the FADC directly.
> 
> I have extracted some parts of the ADC datasheet concerning 
> the input stage into a document and attach the full data sheet.
> 
> Could you have a look and let me know if the ASIC can drive 
> the FADC without buffering.
> 
> The saving in power and layout etc is quite large, about 46W 
> per FEE module.
> Thanks
> Patrick
> 
>