AIDA Meeting - STFC DL - 12 November 2008
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Present: IL, PCS, TD, ZL, JS, RDP, SR
	DB, SLT

Apologies:

Summary of meeting
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Mechanical 

Design concept per discussion at October '08 meeting

Thermal pad shown as purple rectangles in slide 2 (bottom left) - small
squares RF screen for ASICs

Population of SOIC components mezzanine STFC DL - need to maintain 
(45 deg, i.e. 4mm clearance for 4mm high component) clearance for wire 
bonding of ASICs at STFC RAL

Assembly order: SOIC - ASIC - wirebonding - input connector (press to fit)

Operating temp +40 deg C cf. ambient, i.e. ~60-65 deg C

JS/TD/PCS input cabling configuration

ASIC 1

output buffer - linear

Progress on recovery time, reset and recovery
Decay - decay correlations will be limited by peaking time (0.5-8.5us
CR-RC shaper CR=RC=peaking time) ~ peaking time + 4-6us? Reset sequence
programmable

Dec 1 submission

risk of unexpected problems during top level checking
next deadline week 3/4 Jan '09

SLT will e-mail review on or around Nov 21 

FEE

priority to analogue readout (reduced spec FEE)
digital readout requires higher spec

TD to help with spec for input cable

Dummy mezzanine to provide test inputs to FEE64

mid-Jan - end-Feb VHDL development by PCS

Gantt chart
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PCS -> input
	hardware
	VHDL

Inout needed from
John/Dave/Rob -> mechanical
Vic -> software
Me -> DSSD, kapton cable

Commissioning test
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Next meeting: 9.12.08 @ 13.30