AIDA Meeting - STFC RAL 16 September 2010
-----------------------------------------

Present: SLT, PCS, ZL, TD, IL
Apologies: 

Summary of meeting
------------------

ASIC
----

SLT tests
---------
Test input up to 4V via few 100pF => ~ nC

page 1
+ input
first 4 peaks (diodes not ON), second 4 peaks (diodes ON) @ ~gain x ~0.3
losing charge to substrate

page 3
- input
peaks to right @ correct gain
other peaks to left show higher gain

page 5
slow down input from 10ns -> ~ 500ns
page 6
INL ~ 0.1-0.2%

DB analysis/modelling
---------------------

new design LEC/HEC switch

INL dependent on t_r, power supply, C_D
low C_D, 3.3V cf. 4V and t_r < 100ns => poor INL

design AIDA 7.5mm x 8mm
design 2 12mm x 3mm require ~200 dies

reticule square max 22mm x 22mm rectangle max 26mm x 

* SLT - Paul Booker to quote production slice & dice run
        will request early delivery (at higher cost) of first Si wafer
        to speed early production of first mezaanine + ASIC modules
 
* SLT to provide design finalisation review next Thu 23 sep 2010

FEE
---

JT/PCS working on switched-mode PSU solution to meet cost requirements

to test mezzanine with switch-mode + linear regulators tomorrow

request +2 populated mezzanines to increase stock from 2 to 4
 
DAQ/software
------------

Mechanical Design
-----------------

Commissioning Tests 
-------------------

Other
-----

Next meeting: 13.30 Thu 14 Oct 2010