AIDA Meeting - STFC DL 17 November 2011
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Present: TD, PCS, PM, RDP, VFEP
Apologies: IL

Summary of meeting
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Commissioning Tests 
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ASIC
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+2 assembled production ASIC mezzanines

Paul Booker has setup alignment jig and programmed bonder for 4 dies
SLT has said to Paul Booker to prioritise bulk of modules to be completed
this CY

PCS notes mech problem with Cu blocks but will forward PCB mezzanines
to SLT at RAL 

We will require 16+2 production FEE mezzanines by end of CY

TD to contact IL & SLT to calrify how to fund/resource Paul Booker
at RAL


FEE
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3x MACB (clock distributor) modules - requires PCB mods
Requested quotes for 16 PCBs - Edinburgh EW for assembly
in Jan/Feb 2012

FEE64 firmware development Xilinx 13.2 
DMA (data path to memory) - separate paths for MUX and sampling ADC
readouts
Time warps *may* be resolved/understood

Next task - sampling ADC readout

FEE Cu blocks need rail slot widened by 50um
2 to be mod'd immediately to check fix

Others to be queued asap
 
Can now remotely control FEE PSU
 
DAQ/software
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VFEP requests *offline* test with multiple FEEs at GSI of date merge to 
MBS *prior* to any scheduled run

Mechanical Design
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All up assembly from Liverpool w/shop to be ready end of Jan 2012
Integration with water chiller etc Feb 2012

Other
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Next meeting: 10.30 Wed 18 Jan 2012