From S.L.Thomas@rl.ac.uk Wed Sep 26 20:45:44 2007 Date: Thu, 6 Sep 2007 17:16:27 +0100 From: "Thomas, SL (Stephen)" To: "Coleman-Smith, PJ (Patrick)" Cc: Thomas Davinson Subject: RE: AIDA FEE specification Patrick It is good that you have included provision for direct ASIC cooling in the diagram. The power could be quite high, maybe up to 1W per chip. There would need to be some form of encapsulation of the 4 ASICs to protect bond wires - perhaps a package of some kind or a copper box soldered around the ASICs. This would give a flat surface, thermally in contact with the ASICs, onto which the conductive foam would locate. Another approach is build thermal links into the sub-board, to provide a path for heat flow from the ASICs via the mezzanine. The board could have a ground plane with thick copper, thermally connected by multiple vias to the connector area. Steve > -----Original Message----- > From: Coleman-Smith, PJ (Patrick) > Sent: 04 September 2007 15:54 > To: Thomas, SL (Stephen) > Cc: 'Thomas Davinson' > Subject: AIDA FEE specification > > > Hi Steve, > Could you have a look at this and comment, particularly on > the need for ASIC cooling please. > > Please phone me if it doesn't make sense. > > Regards > Patrick >