AIDA Meeting - STFC RAL - 2 October 2009 ---------------------------------------- Present: DB, PCS, TB, JS, RDP, TD, IL, VFEP, PM Apologies: SLT Summary of meeting ------------------ Budget ------ Staff - hours expended but not to permitted +20% overrun Will order 20x Mezzanine cards (STFC) + 20x Cu covers (Liverpool) Assuming >80% yield this should guarantee 6x Mezzanines + spares with 4 working ASICs Computing & network hardware will require 5k Will organise meeting with MP, SLT, DB, PS, IL to discuss potential Feb 2010 engineering run. ASIC ---- Request for assembly drawing for ASIC mezzanine (JS has appropriate drawing in his mech presentation) DB/SLT working on other project(s) until Mezzanine/FEE ready Possibility of shared engineering run with Paul Sellar (RAL) for February 2010. To be explored further. Reset of (buffered) preamplifier output complicates MWD processing as signal is not continuous (per resistive feedback preamplifiers). To be discussed further. Reset by # clock cycles 4-bit programmable (i.e. 1-16 cycles @ 500kHz, 2-32us) DB to find out how much notice Paul Booker requires for bonding ASICs to Mezzanine cards FEE --- 8x Prototype FEE cards delivered Some manufacturing/design issues - resolved ad hoc. At the moment problems configuring Xilinx Virtex 5. Mechanical Design ----------------- 8cm x 8cm prototype enclosure assembly complete Cu ASIC shield quote ~5.4k incl VAT for 30 off Require 3 off complete 2xFEE64 mechanical assemblies Check thermal requirements. Recirculating gas chiller - thermocube from Solid State Coolings systems Design of cooling system for all up system (and cost). Commissioning Tests ------------------- Other ----- Next meeting: Tuesday 11 November 2009