AIDA Meeting - STFC RAL - 30 April 2009 --------------------------------------- Present: TD, SLT PCS, IL, VP, SRA, DS, JS, ZL Apologies: Summary of meeting ------------------ ASIC ---- Few days of *basic* tests Packaged as 40-pin DIP + IMS chip (digital!) tester OK for high thresholds/large signals Power requirements as expected c. 50ns preamp output risetime without load Investigating ASIC bias/direct preamplifier outputs To investigate digital modes So far so good c 4-5 week program ahead Mezzanine design via floorplan SLT/DB need to provide revised dims for mezzanine card by May/week 3 to meet FEE mechanical design timescale. 40-pin package DIL -> DSDG/TBU @ STFC DL for VHDL development (c 6 weeks) FEE --- FEE design proceeding but PCS's time limited uring report period RAM routing almost complete Tasks -> DSDG/TBU ethernet perf optimisation, DMA device, memory test etc Difficult to estimate time to completion - PCS will be better able to estimate at next in meeting 4-5 weeks Mechanical Design ----------------- RDP/SRA/ZL to arrange meeting with DS/JS next week to finalise design concept. Once approved DS should proceed to detailed design work. JS to supply outline jobs for queue at Edinburgh mechanical workshop Commissioning Tests ------------------- NSCL - did not accept proposal GSI - will be told that we expect system availability Aug/Sep '09 and request test beamtime accordingly SRA/ZL to explore options for TAMU - aim for decision and request to TAMU prior to next meeting Other ----- Next meeting: 14.00 Tuesday 9 June 2009 at STFC DL