AIDA Meeting - STFC RAL - 31 July 2008 -------------------------------------- Present: TD, PCS, SRA (via video conference from STFC DL) SLT, DB Apologies: RDP, JS Summary of meeting ------------------ ASIC Design Review Min detectable offset pMOS PH ~10mV ~130keV (~1.5V FSR = 20MeV FSR) nMOS PH ~4mV ~50keV Comparator input offset random variations of comparator offset (3 sigma) of typical offset 30mV requiring increase in global threshold to avoid false triggering global threshold some optimisation/minimiation of offset by design local correction of offset (via 6?-bit DAC from lookup table loaded via serial interface auto at power up) Design model mixed signal 0.35um Add pad (if floorplan space available) for forward-biased diode to measure die temperature, PCS tosupply MAxim part number for control device via I2C SLT to provide floor plan in next week Periodic reset of PH ~10-100ms period, duration ~2us (low deadtime) PH accumulates noise voltages limiting FSR FEE Design Review Calibration Control lines to register to control input capacitors Analogue Ext connection to all ASICs/AFE64 On-board DAC (risetime <=50ns) for 20MeV/1GeV FSR For 20GeV FSR -> via 0.6nF cap to FEE input connector Analogue switch to disconnect DAC test pulse Ext test input to front of FEE FPGA FX70T $500 each Next meeting: 9.10.08