AIDA Meeting - STFC DL - 3 Sepetmber 2009
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Present: IL, PCS, JS, TD, SRA, SLT (via video)
Apologies:

Summary of meeting
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Budget
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Edinburgh - little so far
            expect to spend Si NRE & prototype DSSSDs by end of '09
            production DSSSDs by June 2010

STFC - manpower budget spent (grade rather hours logged/booked)
       capital spend to date £39k
       
       ASIC MPW run uneconomic for >100-200 dies
            production (dedicated) run 80kEuro 
            guarantee 2 wafers, probably 5-6 delivered
            8" wafer 7.5mm x 8mm 90% yield
            ~500 dies per wafer

       projected overspend £61k
       principal problem budget based upon 128 channel FEE compared to
       actual 64 channel FEE

Liverpool - not known
       RDP/SRA to provide data to IL

       FEE production run within 09/10 FY
       ASIC production outwith 09/10 FY
       
       IL to produce ideal spend profile for discussion with STFC
       
ASIC
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SLT working on ASIC documentation
       based on current testing at nominal (default) settings
       
DB will produce report summarising tests to date

SLT returning from vacation/DB now on vacation

FEE
---

Mezzanine - layout complete, tracked and checked
            Paul Booker has checked that dies are bondable
            awaits approval from SLT/JS
            production run ~30 units (~£100 per unit)
            8-10 min requirement
            90% ASIC yield => 66% mezzanine yield (4 working ASICs)
                           => x2 + mechanical samples
            IL/PCS to check whether Liverpool has hi-access bonder
            prototype bonding most probably at RAL

FEE64 PCB   2(Lycca)+6(AIDA)+1(DSDG) assembled units return Sep 21
            + unpopulated PCBs as mechanical samples

October 31 - milestone - deadline to proceed to in-beam test

Plan to use GREAT metronome (requires VME crate + CPU) 
but FEE uses LVDS/HDMI 19-pin so requires (at min) an
adaptor.

Propose PCS produces schematic -> layout/routing/production at Edinburgh
or Liverpool

PCS purchased -5V/+30V PSU for max. 4 FEE cards

Mechanical Design
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Paul Booker - bonding _and_ cover installation

Modify mezzanine design - move Caps to rear side of PCB 

Width of FEE card should reduced from 80mm -> 78mm for production run

Revised drawings of ASIC cover blocks by end of month - production
run of ~30 at Edinburgh or Liverpool. 

Commissioning Tests 
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Other
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Next meeting: 11.00 Friday 2 October