AIDA Meeting - CCLRC DL - 8 December 2006 ----------------------------------------- Present: Tom Davinson, Zhong Liu Edinburgh Rob Page Liverpool Ian Lazarus CCLRC DL Stephen Thomas, Mark Prydderch (video link) CCLRC RAL Summary of meeting ------------------ Discussion of draft AIDA technical specification. As presented there appears to be the possibility that events >20MeV and less than the minimum high energy comparator level (c. 400MeV) result in overload of the low energy chain with no reset, e.g. crosstalk/coupling in strips adjacent to the high energy implant. There will probably be a front end comparator to detect _any_ event >20MeV. Figure 2 of the draft technical specification showing a schematic of the ASIC is misleading. For example it does not show the distribution of reset signals to various parts of the low/intermediate and high energy chains. Sampling ADC for high energy range is optional. Can use conventional shaper, peak detect, MUX, ADC chain, i.e. 2x Octal sampling ADCs low/intermediate energy, 1x ADC for high energy - may need to for space, cost reasons. Discussion of pulse pair resolution of the low energy comparators. If we use the conventional shaper, peak detect, MUX and ADC chain then the required pulse pair resolution is determined by the readout time (~5-10us). For DSP a digital CFD will be implemented - IL has already demonstrated a pulse pair resolution of ~0.5-1us for Ge detectors sampled at 80MHz. The CFD will be used to trigger access to a circular data buffer when an event is detected. It is envisaged that the FPGA will supply an energy value (e.g. from MWD + BLR algorithm) plus 10us (say) of sampled data for further analysis. Fast decay-decay correlations will require further processing of the sampled data. TD requested estimates of time jitter of low/intermediate and high energy comparators. SLT. SLT presentation of AIDA Design Study: Overload & Crosstalk Further refinement of design study model to include proposed ac coupling of detector, bias resistors, preamp & shaper resets etc. x1000 overload recovery in few us. Discussion of crosstalk issues. Crosstalk matches calculations in draft technical specification but simulation also shows slow recovery which may indicate rate limitations - lower coupling capacitance, faster recovery, higher crosstalk. TD to investigate probable rates in more detail. Discussion of MSL quotations 5506A/B 5506A (6" wafer) £190k + VAT, 5506B (4" wafer) £200k + VAT. Current budget for silicon is £190k + VAT. Low risk option is 4" for similar cost to 6". RDP reports that increased number of series bonds required for 4" should not be a significant issue. Not necesaary to make decision yet and MSL will be producing a 6"/1mm detector for another customer in Spring 2007. Discussion of LEB Collaboration meeting 23-24.11.06 Summary of infrastructure requirements to be submitted to Berta Rubio/Zsolt Podolyak asap. TD What Next? Current technical specification (with some caveats) provides sufficient detail. RAL will work up internal (controlled) engineering specification document January/February. IL will check available engineering effort for FEE PCB by January. Technical specification release for more detailed engineering work envisaged early 2007. Edinburgh acquiring AVX capacitor arrays (20nF/100V) for test of voltage rating. Tests should examine lifetime issues when overrating capactor to 200V. ZL undertaking Moccadi simulations of expected implantation profiles at image plane of FRS for various FRS operation modes and exemplar experiments. Next meeting 20 February 2006, CCLRC RAL T.Davinson - 9 December 2006