AIDA Meeting - STFC RAL - 9 January 2008
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Present: Patrick Coleman-Smith
	 Ian lazarus
         Thomas Davinson
	 Zhong Liu
         Davide Braga
         Stephen L.Thomas
         John Simpson, Sami Rinta-Antila, Rob Page, Patrick Coleman-Smith

Summary of meeting
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TD
--
Cap tests
Det test
ADC tests

JS
--

+4pi n

+Ge 
1) RISING Cluster with current frame
   check compat
2) 'other' Ge

+Fast timing
1) LaBr3

+TAS

+ToF
no UK bid
far far away

HiSPEC/DeSPEC meeting bang drum!
early Feb meeting at DL with RDP/DS for design

PCS FEE
-------

128 channel 50W!!!
mostly ADC + single/differential receiver

PCS currently available from May
SLT prob 100-200 mW/ASIC certainly <500mW/ASIC (but only if _necessary_)


ASIC

3 month ASIC production run
submission late April (optimistic scenario), june may be more realistic
PCS needs ASIC manual + details of functionality of FPGA/VHDL

provision to switch off individual channels
per channel threshold/offset
per ASIC shaping time

by May '08 design of mezannine/pinout -> PCS for FEE design
check output range/swing of peak detect
                            preamplifier



request time jitter

Next meeting DL 3.3.08