qAIDA Meeting - STFC RAL - 9 October 2008 ---------------------------------------- Present: TD, ZL, PCS, IL, SRA, RDP, DS , JS (via video conference from STFC DL) SLT, DB Apologies: JS Summary of meeting ------------------ ASIC Design Review Min disc level ~10keV (~7mV) V-hysteresis ~10mV Reset variable from 1-16 clock cycles (clock cycle = 2us) Much custom layout cf. expected re-cycling of previous design blocks Analogue outputs single-ended (not enough space of RHS of die for additional pads required). Global OR output not yet included! FEE Design Review Cover required for ASICS + connectors of mezzanine PCB for mechanical and electrical screening. Important thing is tight fit of cover within central area of ASIC to minimise stray cap. (~fF sensitivity) Cover material OF Copper Requires jig for cover assembly _and_ input connector Die attached to substrate by metal(silver)-loaded epoxy Die thickness ~0.7mm, epoxy ~0.03mm Mezz. PCB needs 4 layers Ceramic limited to 1/2 layers ... better thermal flow, poorer track density FR4 preferred provided heat can be managed require heavy duty ground plane (~30-40um Cu) to aid heat flow per ASIC 3.3V/0.5A PCS to check with SLT/DB design of buffer (input impedance etc.) Power supply should permit variations from nominal 3.3V ASIC supply TD to do revised project plan essential in-beam tests Next meeting: 12.11.08 STFC DL 11.00