AIDA Meeting - STFC RAL - 11 February 2009
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Present: TD, ZL, RDP (by phone), PCS, IL
	SLT, DB (via video link)

Apologies: SRA, JS, DS

Summary of meeting
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ASIC
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Prototype design submitted - HURRAH!
IMEC design checks OK - HURRAH!
@ foundry + 12 weeks delivery

Ceramic ASIC carrier layout issues and pad decoupling discussed.
Important that off chip resistance < on chip resistance: target
on chip resistnace ~10mOhm. Careful design/layout required.

Current priority documentation, sims related to optimal layout
of module, and pad definitions.

DB/SLT will supply PCS with documentation/specifications of pads
as soon as possible.

FEE
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For current schedule PCB layout should be completed March 9

GSI
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ZL submitted AIDA prototype test proposal to G-PAC. Currently GSI
expect *1* running period for FRS in 2009 - July-September period

Other
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IL reported that another STFC group (@ DL) wishes to use FEE with
XSTRIP/XSTRIP2 ASIC. Other group would supply VHDL engineering effort
in exchange for access. IL has disccused with Marcus French and John
Simpson - currently sorting out details. Win-win.

Next meeting: 13.00-15.00 Wednesday 18 March 2009 at STFC DL