AIDA Meeting - STFC DL - 14 January 2009 ---------------------------------------- Present: TD, ZL, RDP, SRA, JS, PCS, IL, SLT, DB Apologies: Summary of meeting ------------------ ASIC ---- 'A week is a long time in chip design ...' Steve Thomas, STFC RAL Review of (almost) complete top-level design Internal design review next week Finalise ASIC spec and pin out Pin out to PCS early next week SLT will add diode (2 pads) to ASIC design to be interface to a Maxim IC PCS requires ASICs 8x FEE cards => 32 ASICs SLT requires 4 for ab initio tests => 4 ASICs Request quote for ASIC NRE plus 50 or 100 (guaranteed) ASIC dies AMS 0.35um 4 level metal (std voltage) +13 weeks delivery Any necessary packaging at STFC RAL FEE --- Bill of materials request for quotation Lead time 6-10 weeks Materials & assembly £19200+VAT / £18500+VAT for 8x FEE64 does not include NRE PCB, mezzanine, mechanics and (a few) minor components FEE card + mezzanine availabel +15weeks from ASIC submission Edinburgh to provide test input mezzanine card once mezaanine pinout is finalised STFC RAL bond prototype ASICs to mezzanine TBD: assembly order - PCB - mezzanine - ASIC wire bonding - press-fit FEE input connector Mechanics --------- Commissioning runs ------------------ GSI --- Two possible slots: June/July or November/December Use Xe or U beams Generate short-lived nuclei Te/I or sub-U TD/RDP/SRA to comment on draft by Friday 16 January Circulate to DESPEC next week January 31 deadline NSCL ---- Revised draft by Friday 23 January February 26 deadline TAMU ---- RDP to supply list of beta-delay p emitters to SRA/ZL (tomorrow - 15.1.09) SRA/ZL to select ~5 candidates TD will discuss with TAMU to estimate potential yield @ MARS Next meeting: 11 February 2009 13.30 STFC RAL