AIDA Meeting - STFC DL 16 February 2011
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Present: PCS, SLT, MK, ZL, RDP, DS, IL, TD(by phone)
Apologies: 

Summary of meeting
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ASIC
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Dies back from wafer cutting
700+ dies available from 2 wafers (other wafers uncut)
Paul Booker will package 3 test devices (plastic package)
Paul Booker away next week
RAL will have three 4xASIC mezzanine FEE modules to ship tomorrow am to DL
 - delivery Friday 18 Feb 2011
When RAL test devices available basic tests of front end design mods
 - should be completed in c. 2 weeks

FEE
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2 pre-production prototypes have been delivered Feb 10
 - MK testing digital aspects of FEE64
 - first pass check of power system looks OK
 - started analogue tests yesterday
Mezzanines delivered and sent to RAL
Still awaiting delivery of additional 6x FEE64 PCBs (production shortfall)
and a further 7x FEE64 PCBs to replace PCBs which failed QA acceptance
at Jaltek.
Jaltek currently scheduled to start production next Monday 21 February

DAQ/software
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LYCCA test (1x DSSSD, 1x FEE64) test - May 4-8, 2011.
IL/VFEP liaising with Nick Kurz (GSI) - based on VME scalers
and supplied common clock.
ZL to develop/investigate user online processing.
IL currently writing up concept discussions prior
to circulation - will discuss further with Nick Kurz 
during NUSTAR week (w/c 28.2.11).

Mechanical Design
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Commissioning Tests 
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Other
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Next meeting: 13.30 14.3.11