AIDA Meeting - CCLRC RAL - 20 February 2007 ------------------------------------------- Present: Tom Davinson, Zhong Liu Edinburgh Sammi ? (via video link) Liverpool Ian Lazarus CCLRC DL John Simpson, Patrick Coleman-Smith (via video link) Stephen Thomas, Mark Prydderch CCLRC RAL Summary of meeting ------------------ Engineering Specification & IPR ------------------------------- SLT has prepared a draft Engineering Specification for the AIDA ASIC. This will be a controlled document. It represents the agreed engineering specification for the AIDA ASIC and will be formally signed off by RAL and TD (representing the 'customer'). TD to provide updated Gantt project workplan with revised dates; SLT will add additional project milestones to the ASIC workplan. The document will then be circulated for comment and sign off by the end of February 2007. Intellectual property rights (IPR) are discussed in the Engineering Specification document. CCLRC (RAL) retain IPR for the engineering design. In practice, this means that some details of the design technology and methodology will be deemed confidential to CCLRC (RAL) and not published. However, this will not affect or restrict the supply/sale of actual hardware (ASICs) to other *academic* customers. Because of the license conditions attached to the CAD/CAE software packages used by CCLRC RAL, supply/sale to commercial organisations will need to be handled differently. Technical Specification ----------------------- Manpower -------- SLT began detailed engineering work on the AIDA ASIC in January 2007. He will continue to work on this (and other) projects over the next few months. Pete Murray will also work on this (and other) projects during this period too - SLT & PM will interchange as required. They expect to have a realistic prototype engineering design available for review in May 2007. PCS will spend 20% of his time on the project to June 30. From July 1 he will work fulltime on the AIDA FEE motherboard design. Prototype --------- MP will review ASIC prototype and production costs. Prototype ASIC dies will be packaged for basic functional tests at CCLRC RAL. Expectation is that yield will be >90% so wafer probe tests are not expected to be required. CCLRC RAL will produce a Test Specification document (not controlled) prior to Final Design Review. Test to specification will require an operational FEE PCB and DAQ from CCLRC DL. Currently, it is envisaged that the FEE PCB will populated and tested at CCLRC DL. CCLRC RAL will then bond the prototype ASIC dies directly to the PCB. It should be noted that the ultrasonic wire bonding will place some limitations on the height and position of components on the FEE PCB. ASIC Design Study ----------------- SLT presented and discussed a number of preamplifier feedback options (see attached presentation). A 30M resistor (200u x 200u @ 1.2k per unit square Poly2) is actually a realistic possibility but there are problems with the effects of parasitic capacitive coupling to the substrate so that it in fact behaves like a distributed RC-network. NMOS and PMOS transistor feedback options also discussed. No preferred option at this stage. Moccadi simulations ------------------- ZL presented the results of a series of Moccadi simulations of the expected implantation profiles at the image plane of the SuperFRS for various operation modes and exemplar experiments (see attached presentation). Conclude that the maximum rate per strip will be ~100Hz. ZL notes that the design of the SuperFRS is ongoing and that the simulations should be considered representative rather than definitive at this time. AC coupling ----------- Edinburgh has acquired 15nF/100V/X7R/0612 SOIC capacitor arrays from AVX and has designed and manufactured a test PCB. The capacitor arrays will be tested for leakage current as a function of bias and over-bias (200V+), and long term soak tests will be undertaken to determine how accurate/conservative the manufacturer's specifications are. http://www.avx.com/docs/masterpubs/smccp.pdf (pp. 48-52) Sampling ADC ------------ Edinburgh will acquire an Analog Devices evaluation kit and support hardware to test the AD9222(12-bit) and AD9252(14-bit) octal, 50MSPS ADCs. The evaluation kit supplied will need to be modified to support single-ended, dc coupling of a preamplifier signal to the ADC rather than the default transformer coupling. Test results will be used to inform the FEE design. Next meeting ------------ 11.00 15 May 2007, CCLRC DL T.Davinson - 24 February 2007