AIDA Meeting - STFC DL 27 January 2010 -------------------------------------- Present: PCS, ZL, JS, VFEP, RDP, TD, DB, IL, SLT (by video) Apologies: Summary of meeting ------------------ ASIC ---- 5x mezzanine cards, 5x Cu blocks, 5x Dow Corning foam (5 complete kits) sent to RAL. Two complete modules returned from RAL to DL with 4x ASICS each Example of prototype test uses PC cooling tower+fan which decreases Si die temp by ~5 deg C - cooling system appears to work OK FEE --- 2x FEE boards operational at same rev state +6 more in various states Linux OS almost ready for cache on FEE ('golden copy') from which it would normally boot - PCS/VFEP to review with DDG tomorrow (28.1.10) Clock unit submitted for manufacture - est. delivery Feb 15 DAQ/software ------------ Mechanical Design ----------------- Complete prototype assembly for Mezzanine available Support plates for FEE now available (ready for assembly) Action TD - Kapton PCB sample to JS/DS when available Check cable handling for simplest mechanical configuration (presentation - slide 3 - LHS image) Current problem with integrated ASIC/Mezzanine/FEE is lack of digital activity (trigger o/p, signal reset etc) do not operate. Commissioning Tests ------------------- Beam request for 3-4days beam from mid-March at MARS submitted to TAMU scheduler. Other ----- Next meeting: TBA following TAMU schedule announcement