Summary of Meeting Micron Semiconductor Ltd
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Date:		6 July 2006
Location:	Micron Semiconductor Ltd., Lancing
Present:	TD, Colin Wilburn, Susanne Walsh

1mm Si Wafers
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4" technology

	Well established

	Major caveat - supply of wafers with the required resistivity
		and uniformity unpredictable

	20kOhm.cm (nominal) wafers in stock at date

6" technology

	No (successful) devices to date

	No development/test structure masks available for 6"
		Causes of failure uncertain but presumed resistivity uniformity
		c. £20k required for masks

	20kOhm.cm (nominal) wafers in stock at date - quality uncertain but 
	presumed insufficient

Options

	Pursue development of 6"/1mm 
		investment required
		moderate-high development risk
		wafer supply risk high - delays++

	Pursue development of 6"/<1mm
		0.4 - 0.7mm devices already produced
		moderate development risk
		wafer supply risk moderate - delays+
		probably lowest total array cost
		more suppliers - MSL, Hammamatsu, SI, Canberra/Eurisys?
		can we achieve sufficient stopping power?

	Pursue development of 4"/1mm
		use 4cm x 8cm DSSSDs (_not_ 8cm x 8cm)
		low development risk
		wafer supply risk moderate - delays
		number of wafers to be processed doubles - increased total array cost

		+--+--+--+--+--+--+
		|  |  |  |  |  |  |	5 sets series bonds
		|  |  |  |  |  |  |
		+--+--+--+--+--+--+

		or

		+-----+-----+-----+
		|     |     |     |	2 sets series bonds
                +-----+-----+-----+
		|     |     |     |
		+-----+-----+-----+

		Former probably mechanically more stable - all wafers supported
		by opposite sides of PCB

		Multi-guard ring structures and wafer cut clearance c. 1.5mm
 		from active area, i.e. gaps in active area of c. 3mm

Integrated components
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Polysilicon bias resistors

		Reliable
		10-100M available
		Excellent yield

AC coupling

		100pF/100V nominal
		increased dead layer thickness
		expectation c. 1 fault per side per wafer

Options

		discrete surface mount components
			to nominal 0.625mm pitch?
			0603 package 1.6mm x 0.8mm x 0.9mm, 50V max rating?
			0805 package 2mm x 1.25mm x 1.25mm, 200V max rating?
			1206 package 3.2mm x 1.6mm x 1.68mm, 500V max rating?
			location DSSSD PCB or FEE?

		IC coupling capacitor package?
			location DSSSD PCB or FEE?


Packaging
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Assemblies with Kapton PCBs well established.

Pre-formed and hot cured kapton PCBs used for minimal overhead packaging
- see BB/7 IKS package.

In principle, PCB dimensions need only exceed wafer dimensions by c.2-3mm.