AIDA Meeting - STFC DL 30 November 2010 --------------------------------------- Present: IL, PCS, PS, RDP, JS, SLT TD, ZL (by phone) Apologies: Summary of meeting ------------------ ASIC ---- SLT/DB will queue wafer slicing ~2 weeks in advance. Paul Booker will be given ~2 weeks notice of prototype and production batch jobs and anticipate that PB will focus on this job for ~1 week as necessary. ASIC delivery still expected early January - late December possible, AMS will advise shortly before delivery. Mezzanine PCB in production. 40 cu blocks ordered. Proto in 2weeks. Production week 1/2011 FEE --- FEE PCB in production. Current FPGA delivery 9.1.11 - Avnet attempting to deliver before Christmas. VHDL work on hold. MK (from DDG) will probably start work on AIDA FEE/VHDL in Jan 2011 PCS to check with JT re-PSUs and availability for testing at DL DAQ/software ------------ Mechanical Design ----------------- RDP/PS to discuss cable harness & PSU size/position with DS/JT Consolidated grant bid ---------------------- Coordination of manpower, capital & travel bids required. Commissioning Tests ------------------- ZL reported that standalone AIDA proposal has been favourably received and rated. There are opportunities to schedule this for the second half of 2011 - we should request beamtime and lobby for this. Christophe Scheidenberger suggested we contact Chiara Nociforo about timestamping. IL will contact Haik Simon about this too. We need to understand *how* to progress development and production of the necessary hardware. Other ----- Next meeting: 13.30 19.1.11